This invention relates to data processing techniques and more particularly relates to such techniques in which the data is shifted.
In U.S. Pat. No. 3,818,203, issued June 18, 1974, the applicants described an improved matrix shifter capable of performing multibit shifts in an amount of time independent of the number of shifts performed. This is accomplished by the use of a connection matrix and selective gating of input lines to output lines, thereby introducing only one gate delay from input to output of data. The applicants have discovered that this matrix shifter can be combined with additional digital apparatus in order to substantially reduce the time previously required in order to perform arithmetic and shifting operations on digital data.
According to one feature of the invention, the matrix shifter can be combined with an arithmetic and logic unit, as well as a memory or register file which is capable of reading two digital numbers stored in the file onto two separate output busses. The digital numbers read out of the register file are transmitted to the arithmetic and logic unit and to the matrix shifter before the resulting digital number is stored. By using this architecture, digital numbers can be subjected to an arithmetic operation and multibit shift during a single pass through the arithmetic and logic unit and matrix shifter.
According to another feature of the present invention, techniques of the above-described type can be improved by using simultaneous access memories or register files in which two different registers are simultaneously accessed through output ports and perform a write to one of the registers. By using this feature, the time required for reading two numbers from different registers, performing an arithmetic operation on the numbers which creates a resultant number and performing a multibit shift on the resultant number is drastically reduced. This feature permits the execution of register dyadic operations in a single cycle with a single clock pulse.
The applicants have found that the foregoing techniques can be used to improve the execution of dyadic fixed point operations, algorithms, such as multiply and divide, floating point operations and bit maneuvering. If the above-described techniques are used, these operations can be performed with a degree of speed and simplicity heretofore unavailable by using more conventional cumputer architecture.